The boundary-scan is an electrical test method that can test complex circuits in an assembled PCB (e.g. Ball Grid Arrays, short: BGAs) and requires only four lines to do so.
In boundary-scan testing, the environment within a circuit is tested – this is also referred to as “boundary-path scanning“.
A boundary-scan-IC contains control logic in addition to its core logic. This consists of the Test-Access-Port (TAP) and the boundary scan cells. These cells are combined into a shift register with parallel inputs and outputs and form a serial scan path. Stimulation and readout of the cells is performed by the test access port (TAP). The IC is controlled with four signals via the JTAG port (test bus).
With this test method, assemblies without test pads can be tested quickly and reliably even from prototype status.
A wide range of options for structural or functional tests are provided – a combination of the various boundary-scan test types allows faults in the assembly to be localized quickly and reliably.
The result: very high test coverage with minimal adaptation required!
For reasons of product liability, careful testing of electronic assemblies is essential. Zero-defect productions are a pipe dream, but not always feasible.
Due to increasing component densities, shrinking component sizes and the advent of multilayer PCBs, inspection procedures using conventional methods are becoming considerably more difficult. As a result, there is often not enough space for test points on the package surfaces, so their number must be reduced – but at the same time, no test coverage must be lost.
With boundary-scan, the number of test points required on an assembly can be reduced or eliminated, saving space and simplifying layout design. The process was developed to enable structural testing even in the face of miniaturization.
Boundary-scan is very easy to adapt universally, offers very high test coverage and is time and cost efficient.
Tests generated during the design phase can still be used in the later product phase. Consequently, tests that have already been generated for design verification can be adopted for prototype debuggingand for production testing.
This is an important advantage, since especially in the development of electronic assemblies, their later testability should also be planned for. This reduces the test effort and diagnostic times to a minimum.
The individual test points, which were previously contacted with needles, are included in the boundary scan as additional logic in the integrated circuit (IC): This logic is called boundary-scan cell or electronic nail.
Access to the boundary-scan cells is enabled by the additional control unit TAP (Test Access Port). Access to the boundary-scan cells is enabled by the additional control unit TAP (Test Access Port). The TAP function is in turn defined by three control signals: TCK (Test Clock), TMS (Test Mode Select), TRST (Test Reset). Simultaneously, the TDI (Test Data Input) and TDO (Test Data Output) signals switch the boundary-scan cells into a serial shift chain.
Via this shift chain, signals are then placed on the DUT and measured, depending on the control signals and the selected test function. Test points and needles are no longer required.
Once test access to the boundary-scan function is established, numerous tests can be performed.
However, these test capabilities must be integrated into the design by the assembly’s developer: For example, the board must be provided with a JTAG interface and the boundary-scan ICs must be connected.
We would be pleased to inform you about further design rules for error-free operation of boundary-scan assembly testing.
Access to the boundary-scan function enables various types of tests to be performed.
Ideally, the test procedure can also be used to perform device programming of e.g. flashes and PLDs (programmable logic devices) within the circuit. Furthermore, cluster tests can also be used to test non-boundary-scan devices. If the device under test has different interfaces, additional test hardware can be integrated into the test process.
We are a certified partner of JTAG Technologies for boundary-scan applications and primarily use these systems.
In addition, we offer testing using boundary-scan equipment from GÖPEL electronic GmbH.
By choosing these systems we guarantee you a high defect coverage as well as time and cost efficient processes.
On your behalf, we carry out the appropriate tests for your individual needs.
Test application creation
Test with JTAG Technologies and Göpel systems
Certified partner of the company JTAG-Technologies
Testing of IC devices like BGAs, QFNs
Short test times
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